1. Field of the Invention
This present invention relates to a processor for performing convolutional interleaving/de-interleaving on data symbols; especially, the processor performs convolution interleaving on original data symbols and then convolution de-interleaving on the convolution interleaving data symbols to obtain the complete original data symbols.
2. Description of the Prior Art
The main objective of the system of interleaving/de-interleaving is to reduce burst error effect, which occurs during the transmission process, so as to decrease transmission data error. In the prior art, the technique of interleaving/de-interleaving data symbol uses the reading/writing of data symbols to perform the function of interleaving/de-interleaving data symbols. A schematic diagram of the method of the block interleaving/de-interleaving data symbol in the prior art is shown in FIG. 1(a) and FIG. 1(b).
In another prior art, the technique of interleaving/de-interleaving is the technique of convolution interleaving/de-interleaving. Compared with the method of block interleaving/de-interleaving, this method can utilize less registers to achieve the purpose of interleaving/de-interleaving data symbols. As shown in FIG. 2, FIG. 2(a) is a schematic diagram of the embodiment of convolution interleaving. The data matrixes obtain delay through several registers to achieve the purpose of interleaving data symbol. When I number of data symbols (X0, X1, X2 . . . X1-1) are first written into the memory, because the register causes the delay effect, only the value X0 is being interleaved in the beginning. By repeating the above steps, each data symbol can be interleaved according to the sequence. The reverse method is used to perform de-interleaving. As shown in FIG. 2(b), FIG. 2(b) is the schematic diagram of the embodiment of convolution de-interleaving. De-interleaving is performed on the interleaved data symbols by the opposite arrangement of the registers.
However, the method of utilizing registers to perform convolution interleaving/de-interleaving data symbol by needs larger hardware circuit. The method is not economical. In another prior art, the memory is used as the processor for performing convolution interleaving/de-interleaving data symbol, which can save hardware circuit as compared with utilizing registers. However, this method involves complicated address operation; the operation of the writing address is different from that of the storing address, and the complicated relation among column, row, and block must be put into consideration. The memory capacity needs to double in order to simplify address operation.
Therefore, the main objective of the present invention is to provide a processor for performing convolution interleaving/de-interleaving of data symbols. It further provides the method for saving memory capacity and simplifying complicated operation to solve the problem in the prior art.